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The SATA Host Core is available for integration into host FPGA designs to provide an industry-compliant SATA 1.5-Gbps, SATA 3.0-Gbps, and SATA 6.0-Gbps interface. Serial ATA (SATA) are computer bus standards that have the primary function of transferring data (directly or otherwise) between the FPGA and mass storage devices such as a hard disk. SATA host controller along with AHCI controller enables the software to communicate with the SATA drives which are best suited for SOC devices.
Link layer supports primitives such as ALIGN, DMAT, EOF, HOLD, HOLDA, R_ERR, R_IP, R_OK, R_RDY, SOF, SYNC, WTRM, X_RDY
Transport layer supports 32 bit AXI stream interface for Tx and RX towards user interface
Transport layer supports formatting of the FISes and control information based on FIS type
Transport layer reports frame transmission and reception as well as error status
Transport layer supports FISes such as Register FIS, DMA Activate FIS, DMA Setup FIS, Data FIS, PIO Setup FIS, Set Device Bits FIS
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