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SPECIFICATION
- Phy layer consists of Transceiver available in the FPGA which convert the parallel data to serial
- Phy layer supports clock recovery from serial data, 8B/10B encoding and decoding, Byte ordering and word alignment and OOB signalling
- Link layer supports the frame transmission and reception
- Link layer supports frame formation by adding the envelope and frame decomposition by removing envelope from received data
- Link layer supports CRC generation and calculation as well as scrambling and descrambling
- Link layer supports host and device flow control
Link layer supports primitives such as ALIGN, DMAT, EOF, HOLD, HOLDA, R_ERR, R_IP, R_OK, R_RDY, SOF, SYNC, WTRM, X_RDY
Transport layer supports 32 bit AXI stream interface for Tx and RX towards user interface
Transport layer supports formatting of the FISes and control information based on FIS type
Transport layer reports frame transmission and reception as well as error status
Transport layer supports FISes such as Register FIS, DMA Activate FIS, DMA Setup FIS, Data FIS, PIO Setup FIS, Set Device Bits FIS
HIGHLIGHTS
- AHCI controller along with SATA host controller best suits for SOC devices and SATA controller without AHCI layer can be used with Non-SOC FPGA devices
- Controller provides simple AXI streaming TX and RX interface for the communication with the Application layer.
- Supports Native Command Queuing and most of the primitives and FIS types defined in SATA specification.
EVALUATION PLATFORMS
ZCU102 Dev Kit
iWave SATA host controller IP is tested in Zynq MPOSC based devices from AMD/Xilinx using ZCU102 dev kit and iWave’s FMC daughter card. This daughter card is equipped with the SATA connector to test the IP functionality.
KC705 Dev Kit
iWave SATA host controller IP is tested in 7 series FPGA devices from AMD/Xilinx using Kintex 7 based KC705 dev kit and iWave’s FMC daughter card. This daughter card is equipped with the SATA connector to test the IP functionality.
Stratix 10 SX Dev Kit
iWave SATA host controller IP is tested in Stratix 10 based devices from Intel using Stratix 10 SX dev kit and iWave’s FMC daughter card. This daughter card is equipped with the SATA connector to test the IP functionality.
Arria 10 GX Dev Kit
iWave SATA host controller IP is tested in Arria 10 based devices from Intel using A10 GX dev kit and iWave’s FMC daughter card. This daughter card is equipped with the SATA connector to test the IP functionality.
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