	NXP	Xilinx	Intel PSG	Others
HPC		Zynq ZU19/ZU17/ZU11 Zynq ZU7/ZU5/ZU4	Arria10 SOC
SMARC	i.MX8M i.MX8			Qualcomm SD820
Qseven	i.MX8 i.MX8M Mini/Nano i.MX6		Cyclone V SOM	Renesas RZ/G1H Renesas RZ/G1M TI DM8168
SODIMM	i.MX8M Mini/Nano i.MX6 i.MX6 UL/ULL	Zynq7000		Renesas RZ/G1E
SBC & COTS	i.MX8M Plus i.MX8M Mini/Nano i.MX8 i.MX6	Zynq ZU5/ZU4/ZU3/ZU2 Kintex-7 PCIe Card Kintex-7 3U VPX Card	Cyclone V 6U cPCI	Qualcomm SD820 Renesas RZ/G1C FMC Add-On Cards

Telematics Solutions	ARINC818 Solutions	HMI Solutions	Software Solutions
Telematics Control Unit J1939 Heavy Duty OBD Logger OBD II Device V2X Gateway	ARINC818 Recorder ARINC818 Monitor ARINC818 Tester ARINC 818 Video Protocol Analyser ARINC818 to DVI Protocol Converter ARINC818 to HDMI Protocol Converter ARINC 818 Switch IP Core ARINC818-2 IP Core	i.MX6 based iW-G38H HMI series i.MX8 based iW-G39H HMI series	Security IP Suite

ARINC	sFPDP Cores	Storage Cores	Video Processing Cores	Bridge Cores	Legacy Processor Cores
ARINC 818 Switch IP Core ARINC818-2 IP Core ARINC-664/AFDX IP	Serial FPDP (sFPDP)	SD / SDIO Host Controller 3.0 NAND Flash Controller SD Memory Slave Controller SDIO Slave Controller SATA Host Controller eMMC Host Controller	Video DeInterlacer Color Space Conversion Chroma Resampler Alpha Blender Video Scaler	VME Slave IP Core (VME to AXI Bridge) PCI Controller PCIe to SD/MMC Bridge SDIO to UART Controller SATA 3.0 Bridge Controller	80188EB Processor 80188XL Processor 80186XL Processor 80186EC Processor 8530 Multi-Protocol Controller 8251 SCU 8254 Timer 8259A ICU 8237 DMA

SATA Host Controller

The SATA Host Core is available for integration into host FPGA designs to provide an industry- compliant SATA 1.5-Gbps, SATA 3.0-Gbps and SATA 6.0-Gbps interface. Serial ATA (SATA) are computer bus standards that have the primary function of transferring data (directly or otherwise) between the FPGA and mass storage devices such as hard disk.

Categories: FPGA IP Cores, Storage Cores

Downloads

Documents

Specification

- Phy layer consists of Transceiver available in the FPGA which convert the parallel data to serial
- Phy layer supports clock recovery from serial data, 8B/10B encoding and decoding, Byte ordering and word alignment and OOB signalling
- Link layer supports the frame transmission and reception
- Link layer supports frame formation by adding the envelope and frame decomposition by removing envelope from received data
- Link layer supports CRC generation and calculation as well as scrambling and descrambling
- Link layer supports host and device flow control
- Link layer supports primitives such as ALIGN, DMAT, EOF, HOLD, HOLDA, R_ERR, R_IP, R_OK, R_RDY, SOF, SYNC, WTRM, X_RDY
- Transport layer supports 32 bit AXI stream interface for Tx and RX towards user interface
- Transport layer supports formatting of the FISes and control information based on FIS type
- Transport layer reports frame transmission and reception as well as error status
- Transport layer supports FISes such as Register FIS, DMA Activate FIS, DMA Setup FIS, Data FIS, PIO Setup FIS, Set Device Bits FIS

HIGHLIGHTS

Controller provides simple AXI streaming TX and RX interface for the communication with Application layer.
Supports Native Command Queuing and most of the primitives and FIS types defined in SATA specification.

Others

SATA Host Controller

SATA Host Controller

Downloads

Documents

Xilinx Evaluation Kit

Intel Evaluation Kit

Mircochip Evaluation Kit

Specification

HIGHLIGHTS

Related products

SD / SDIO Host Controller 3.0

SD / SDIO Host Controller 3.0

SD Memory Slave Controller

SD Memory Slave Controller

NAND Flash Controller

NAND Flash Controller

eMMC Host Controller

eMMC Host Controller

SDIO Slave Controller

SDIO Slave Controller