Specification

• • Phy layer consists of Transceiver available in the FPGA which convert the parallel data to serial
  • Phy layer supports clock recovery from serial data, 8B/10B encoding and decoding, Byte ordering and word alignment and OOB signalling
  • Link layer supports the frame transmission and reception
  • Link layer supports frame formation by adding the envelope and frame decomposition by removing envelope from received data
  • Link layer supports CRC generation and calculation as well as scrambling and descrambling
  • Link layer supports host and device flow control
  • Link layer supports primitives such as ALIGN, DMAT, EOF, HOLD, HOLDA, R_ERR, R_IP, R_OK, R_RDY, SOF, SYNC, WTRM, X_RDY
  • Transport layer supports 32 bit AXI stream interface for Tx and RX towards user interface
  • Transport layer supports formatting of the FISes and control information based on FIS type
  • Transport layer reports frame transmission and reception as well as error status
  • Transport layer supports FISes such as Register FIS, DMA Activate FIS, DMA Setup FIS, Data FIS, PIO Setup FIS, Set Device Bits FIS