Specification

• • Compliant with eMMC Specification Version 5.1
  • Supports Default speed (26Mhz), High speed (52Mhz) mode,
  • HS200, HS400, and HS400 Enhanced mode
  • Supports command queuing engine
  • Supports 1-bit, 4-bit, and 8-bit eMMC modes
  • Supports programmable clock frequency generation to the eMMC card
  • Supports Tuning for HS200 mode
  • Supports Interrupt and ADMA2 transfer mode of operation
  • Individual 4Kbyte data buffer for read and write
  • Cyclic Redundancy Check (CRC) for command and data
  • Supports timeout monitoring for response, data, CRC token & busy
  • Supports a maximum block length of 4K-byte
  • Supports both single block and multi-block data transfer
  • Supports auto CMD12 feature
  • Supports 32-bit AXI4 memory-mapped interface towards host processor for data transfer
  • Supports 32-bit AXI4 lite interface towards host processor for register access