eMMC Host Controller

eMMC Host Controller

iW-eMMC 5.1 Controller interfaces MMC / eMMC card to any processor with a generic interface. The interface towards the eMMC is realized by the eMMC protocol implemented in the controller. The core supports AXI4-Lite interface for the control and status register access and AXI4-MM interface for data transfer through ADMA2 mode.



Xilinx Evaluation Kit

Intel Evaluation Kit

Mircochip Evaluation Kit


    • Compliant with eMMC Specification Version 5.1
    • Supports Default speed (26Mhz), High speed (52Mhz) mode,
    • HS200, HS400, and HS400 Enhanced mode
    • Supports command queuing engine
    • Supports 1-bit, 4-bit, and 8-bit eMMC modes
    • Supports programmable clock frequency generation to the eMMC card
    • Supports Tuning for HS200 mode
    • Supports Interrupt and ADMA2 transfer mode of operation
    • Individual 4Kbyte data buffer for read and write
    • Cyclic Redundancy Check (CRC) for command and data
    • Supports timeout monitoring for response, data, CRC token & busy
    • Supports a maximum block length of 4K-byte
    • Supports both single block and multi-block data transfer
    • Supports auto CMD12 feature
    • Supports 32-bit AXI4 memory-mapped interface towards host processor for data transfer
    • Supports 32-bit AXI4 lite interface towards host processor for register access


  • Compliant with eMMC specification version 5.1
  • Supports HS400 and HS400 ES modes
  • Supports command queuing engine
  • Controller provides a AXI4-lite interface for control & status access and AXI4-MM interface for DMA data transfer


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