Serial FPDP (sFPDP)

Serial FPDP (sFPDP)

sFPDP IP Core is based on ANSI/VITA 17.1-2003 Standards. This IP core provides a relatively simple protocol using maximum available data throughput with a minimum protocol for point-to-point data links. sFPDP links support a wide range of physical interfaces with the most common option being 2.5 gigabits per second multimode fiber.

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Downloads

Xilinx Evaluation Kit

Intel Evaluation Kit

Mircochip Evaluation Kit

Specification

    • Compliant with ANSI/VITA 17.1-2015 Serial FPDP standard
    • Supported link speeds
      • Upto 10Gbuad
    • Data Frames supported
      • Unframed Data
      • Single Frame Data
      • Fixed Size Repeating Frame Data
      • Dynamic Size Repeating Frame Data
    • System Configurations supported
      • Basic System Flow Control
      • Bi-directional Data Flow
      • Copy Mode
      • Copy/Loop Mode
      • Unidirectional support
      • Optional flow control
      • CRC
    • Host-Bus interface
      • Parallel FPDP
    • Configurable parametersTransmit FIFO depth
      • Receive FIFO depth
      • Transmit FIFO watermark to assert SUSPEND output
      • Transmit FIFO watermark for TX FIFO Overflow signal generation
    • Receive FIFO watermark for STOP/GO signal generation

HIGHLIGHTS

  • Serial Front Panel Data Port (sFPDP) IP core for FPGA is based on the ANSI/VITA 17.1-2015 standard. The Serial FPDP standard supports Upto 10Gbuad link speed.

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