SD Memory Slave Controller

SD Memory Slave Controller

Memory Slave Controller IP forms a bridge between the SD host and user interface, enabling the data transfer between each other. This IP will send the response to the SD host depending on the command issued and also communicates with the user through a register interface for control and status. The Controller has two different variants depending on the availability of the processor towards user side. One being the AXI4 -lite or AHB complaint interface for accessing through processor and other is simple general-purpose interface which can be used without the processor.

Downloads

Xilinx Evaluation Kit

Intel Evaluation Kit

Mircochip Evaluation Kit

Specification

    • Compliant with SD Physical Specification Version 2.00
    • Supports 1-bit and 4-bit SD Mode
    • Supports Standard and High Capacity operations
    • Supports Default and High Speed Modes of operation
    • Supports all mandatory slave registers set
    • CID Register fields are configured
    • Supports only Standard command set
    • Supports all mandatory SD Command Classes
    • CRC7 checking/generation for Command/Response
    • CRC16 checking/generation for Data transfer
    • Support Maximum block length of 512 bytes
    • Supports Single and Multiple block read and write data transfer
    • Supports Partial and Misalign Block length option
    • SD Memory only implementation
    • IP provides simple and general-purpose interface or AXI4-lite or AHB interface to user application

HIGHLIGHTS

  • Core handles SD bus protocol on the card interface and provides simplified interface to user logic
  • Core handle all the housekeeping tasks by itself without user logic intervention
  • Supports both processor and non-processor environments with two different variants
  • Supports both the standard and High capacity operation

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