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SMARC	i.MX8M Plus i.MX8M i.MX8			Qualcomm SD820
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SODIMM	i.MX8M Mini/Nano i.MX6 i.MX6 UL/ULL	Zynq7000		Renesas RZ/G1E
SBC & COTS	i.MX8M Mini/Nano i.MX8 i.MX6	Zynq ZU5/ZU4/ZU3/ZU2 ZU19/17/11 PCIe SmartNIC Card PCIe Gen3 x8 FMC Module Kintex-7 3U VPX Card	Cyclone V 6U cPCI	Qualcomm SD820 Renesas RZ/G1C FMC Add-On Cards Kintex-7 PCIe Card

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Telematics Gateway V2X Connectivity Hub Telematics Control Unit J1939 Heavy Duty OBD Logger OBD II Device J1939 Protocol Stack UDS Protocol Stack	ARINC 818 Recorder ARINC 818 Monitor ARINC 818 Tester ARINC 818 Analyser ARINC 818 to DVI Converter ARINC 818 to HDMI Converter ARINC 818 Switch IP Core ARINC 818-2 IP Core	i.MX6 based iW-G38H HMI series i.MX8M Mini based iW-G39H HMI series	Security Suite OP-TEE for Android and Linux Wi-Fi Security	Industrial IoT Gateway Corazon-AI Corazon-AI Gen2

ARINC	sFPDP Cores	Storage Cores	Video Processing Cores	Bridge Cores	Legacy Processor Cores
ARINC 818-3 IP Core ARINC 818 Switch IP Core ARINC 818-2 IP Core ARINC 664 P7 IP	Serial FPDP (sFPDP)	SD / SDIO Host Controller 3.0 NAND Flash Controller SD Memory Slave Controller SDIO Slave Controller SATA Host Controller eMMC Host Controller	Video DeInterlacer Color Space Conversion Chroma Resampler Alpha Blender Video Scaler	VME Slave IP Core (VME to AXI Bridge) PCI Controller PCIe to SD/MMC Bridge SDIO to UART Controller SATA 3.0 Bridge Controller	80188EB Processor 80188XL Processor 80186XL Processor 80186EC Processor 8530 Multi-Protocol Controller 8251 SCU 8254 Timer 8259A ICU 8237 DMA

SD Memory Slave Controller

Memory Slave Controller IP forms a bridge between the SD host and user interface, enabling the data transfer between each other. This IP will send the response to the SD host depending on the command issued and also communicates with the user through a register interface for control and status. The Controller has two different variants depending on the availability of the processor towards user side. One being the AXI4 -lite or AHB complaint interface for accessing through processor and other is simple general-purpose interface which can be used without the processor.

Categories: FPGA IP Cores, Storage Cores

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Specification

- Compliant with SD Physical Specification Version 2.00
- Supports 1-bit and 4-bit SD Mode
- Supports Standard and High Capacity operations
- Supports Default and High Speed Modes of operation
- Supports all mandatory slave registers set
- CID Register fields are configured
- Supports only Standard command set
- Supports all mandatory SD Command Classes
- CRC7 checking/generation for Command/Response
- CRC16 checking/generation for Data transfer
- Support Maximum block length of 512 bytes
- Supports Single and Multiple block read and write data transfer
- Supports Partial and Misalign Block length option
- SD Memory only implementation
- IP provides simple and general-purpose interface or AXI4-lite or AHB interface to user application

HIGHLIGHTS

Core handles SD bus protocol on the card interface and provides simplified interface to user logic
Core handle all the housekeeping tasks by itself without user logic intervention
Supports both processor and non-processor environments with two different variants
Supports both the standard and High capacity operation

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SD Memory Slave Controller

SD Memory Slave Controller

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Specification

HIGHLIGHTS

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SD / SDIO Host Controller 3.0

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