NAND Flash Controller

NAND Flash Controller

iW – NAND Host Controller provides an easy interface to access NAND Flash Memory devices. This IP forms a bridge between the NAND flash and User (Processor), enabling to store, read and erase the data in NAND flash. The Controller has two different variants depending on the availability of the processor towards user side. One being the AXI complaint interface for accessing through processor and other is custom interface which can be used without the processor.


Xilinx Evaluation Kit

Intel Evaluation Kit

Mircochip Evaluation Kit


    • 8-bit Asynchronous Interface to NAND device
    • SLC NAND Flash Memory
    • Page Size: Up-to8KByte (Compile time configurable)
    • Commands supported towards NAND Flash Memory: Read, Reset, Page Program, Block Erase and Read Status
    • Separate Chip Select, Write Enable, Read Enable and Ready/Busy for each die and the IO signals are shared between the die
    • ECC Logic: Hamming code used to correct1-bit error and detect2- bit errors
    • 8K-Byte Buffer for write data
    • 8K-Byte Buffer for read data


  • Core is compliant with ONFI specification
  • Supports both processor and non-processor environments with two different variants
  • Controller supports rich set of NAND commands
  • This IP will issue the necessary command address and controls all the necessary actions required to program, erase and read data using NAND flash.

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