NAND Flash Controller IP Core

NAND Flash Controller: A Flash Drive Interface

A NAND Flash Controller IP implements the necessary logic required to interface user data with a NAND Flash memory device. The NAND Flash Controller IP Core performs operations such as Block erase, Page program, and read operations with other mandatory commands which enables access for the NAND device to the user.

iWave’s ONFI 2.0 compliant NAND Flash Controller IP Core is a fully featured, easy-to-use, synthesizable design that can be easily integrated into any SoC or non-SoC FPGA-based platform. Designed to support SLC flash memories, the NAND Flash Controller is flexible to use and implement. The NAND Flash IP Core also adds a faster, asynchronous, or synchronous I/O interface to meet today’s demanding high-performance needs.

The iWave NAND flash IP core allows a designer to quickly and efficiently integrate NAND flash memory functionality into their designs to make use of NAND flash memory capabilities to their design without having to develop the controller logic from scratch. By using an IP core, customers can reduce development time, cost, and risk, and focus on adding value to their end products.

The Key features supported by iWave’s NAND host controller IP are,

  • Compliant with ONFI specification
  • 8 or 16 bit Asynchronous and synchronous Interface to NAND device
  • Supports SLC NAND Flash Memory
  • Page Size: Up to 16K Byte (Compile time configurable)
  • Supports all mandatory commands
  • Separate Chip Select, Write Enable, Read Enable, and Ready/Busy for each die and the IO signals are shared between the die
  • Hamming code or BCH code for ECC logic which can correct up to 8-bit errors per 512 bytes
  • Supports software ECC or ECC by the controller or on-die ECC
  • 16K-Byte Buffer for writing and reading data
  • AXI4-lite interfaces towards the processor for register access
  • AXI4-MM interface towards the processor for data transfer

The NAND Flash Controller IP has been validated on multiple FPGA platforms including Xilinx, Intel, Lattice, and Microchip. Check out the resource utilization document for more information. iWave’s NAND host controller IP has been thoroughly validated with multiple FPGA device families and is well suited for various defense, space, and avionics applications.
NAND Flash Controller IP is available in three variants depending on the availability of the processor on the FPGA device selected by the user.

  • File system using the ARM core of the SOC devices
    • The NAND Linux driver implemented in the ARM core interfaces with the NAND host controller using the AXI4 lite interface for register access and AXI4 memory mapped interface for data transfer.
    • NAND host controller implemented in the FPGA communicates with the NAND devices using the NAND protocol defined as per the ONFI specification.
    • Supports the well-known industry standard flash file systems like JFFS2 and UBI
Zynq 7000 SOC device
  • Simplified Bare-metal driver for non-SoC FPGA devices
    • Bare-metal NAND driver is implemented in ARM core of SOC device or soft core instantiated in non-SOC FPGA device to configure the registers using the AXI4-lite interface, while the AXI4-MM interface is used for data transfer in DMA mode
    • Bare-metal NAND driver supports the NAND device initialization and basic write/read operations required for proving the IP functionality
SOC FPGA device
  • Simple test driver module for non SoC FPGA device
    • Test driver implemented in the FPGA which drives the IP user interface
    • Soft core instantiated in non-SOC FPGA device will drive the test driver to execute the erase, program, and read operations
SOC/ Non SOC FPGA device

iWave offers a “Complete IP Solution” for its NAND Flash Controller IP core, which includes RTL source code, synthesis scripts, a test environment, and documentation, as well as world-class customer support.

With strong competence in FPGA, iWave Systems has demonstrated the seamless integration of iWave’s NAND Flash Controller IP functionality on the Zynq 7000 evaluation kit.

iWave NAND host controller IP Demonstration:

iWave NAND host controller functionalities such as device detection, NAND erase, program, and read operations are demonstrated by using the Zynq 7000 evaluation kit and NAND FMC daughter card. Furthermore, this demo also includes mounting, partitioning and erase, program, and read operations using JFFS2 file system and the UBI file system.

The NAND Linux driver, which is implemented in the Zynq 7000 SoC ARM core, communicates with the NAND host controller via the AXI4 lite interface for register access and the AXI4 memory-mapped interface for data transfer. The NAND host controller implemented in the FPGA communicates with the NAND device present in the FMC daughter card using the ONFI-defined NAND protocol. ARM core debug console is connected to teraterm where we run different commands to test the IP functionality.

Demo description:

FPGA PlatformiWave Zynq 7000 Development Platform
FMC cardAdd on FMC card which houses the Micron NAND device
NAND IP Core for SOC FPGA Device

To watch the demo, click here.

Benefits of using a NAND Flash Controller

Allows seamless integration – NAND flash controller IP is designed to be easily integrated into a variety of systems which can help to reduce the time and cost associated with developing custom memory controllers.
Compatibility & Scalability – NAND flash controller IP can be customized to meet the specific needs of different applications. This can include increasing the number of dies or improving the efficiency of data transfer to support larger capacity devices.
Proven technology – Allows quick and easy into any SoC and non-SoC platforms.
Increased Reliability – NAND flash controller IP includes built-in error correction and detection capabilities, which ensure that data is stored and retrieved accurately. This helps to prevent data corruption, which can occur due to the inherent limitations of NAND flash memory.

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