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OSM	i.MX 91 i.MX 93 i.MX 8X Lite i.MX 8M Plus	RZ/G2UL RZ/Five RZ/A3UL	TI AM62Ax STM32MP13x - Size S STM32MP13x - Size 0
SMARC	i.MX 91 i.MX 95 i.MX 93 i.MX 8M i.MX 8M Plus i.MX 8 Layerscape LS1021A
Qseven	i.MX 8 i.MX 8M Mini/Nano i.MX 6	RZ/G1H RZ/G1M	TI DM8168
SODIMM	i.MX 93 i.MX 91 i.MX 8M Mini/Nano i.MX 6 i.MX 6 UL/ULL	RZ/G1E
SBC	i.MX 91 i.MX 93 i.MX 8XLite i.MX 8M Plus i.MX 8 i.MX 8M Mini/Nano i.MX6	RZ/G2UL RZ/G1C	TI AM62Ax STM32MP13x - Size S STM32MP13x - Size 0

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FPGA SoM	Virtex UltraScale+ Kintex UltraScale+	Arria 10
PCIe Cards	Zynq RFSoC ADC DAC PCIe Card ZU19/17/11 PCIe SmartNIC Card Kintex-7 PCIe Card PCIe to SD 3.0 M.2 Module
VPX Cards/SBC	Kintex UltraScale+ 3U VPX Zynq ZU19/17/11 3U VPX Zynq ZU5/ZU4/ZU3/ZU2 Kintex-7 3U VPX Card
FMC Cards	PCIe Gen3 x8 FMC Module Quad QSFP28 FMC+ Module PCIe Gen3 x16 FMC+ Module FMC Add-On Cards

OSM
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- RZ/G1H
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SoC SoM
FPGA SoM
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VME Slave IP Core (VME to AXI Bridge)

The ANSI/VITA 1.0-1994 or VME64 specification establishes a framework for 8-, 16-, and 32-bit parallel bus computer architectures that can implement single and multiprocessor systems. The VMEbus specification defines an interfacing system used to interconnect microprocessors, data storage, and peripheral control devices in a closely coupled hardware configuration.

iWave’s IP is compliant to ANSI/VITA1.0-1994 and implements the slave configuration of VMEbus data transfer layer consisting of the Data Transfer Bus and the Priority Interrupt Bus modules. This IP can be considered as a VME to AXI bus bridge and can be implemented in any FPGA having interface to a VME Bus Interface.

Categories: FPGA IP Cores, Bridge IP Cores

SPECIFICATION

Compliant with ANSI/VITA 1.0-1994 VME64 Bus Standard
VME to AXI Bus Bridge
VME bus Module Type
- Slave with Priority Based Interrupts
Board Address: Hardware Configurable up to 8 bits
Data Format Supported: 16 bits and 8 bits
Transfer Modes
- Write & Read
- Block Write & Read

Address Modes
- A32 Slave: 09, 0B, 0D and 0F (Data and Block Transfer)
- A24 Slave: 39, 3B, 3D and 3F (Data and Block Transfer)
- A16 Slave: 29 and 2D (Data Access, No Block Transfers)
Block Transfer
- Maximum 256 bytes
User Interface: AXI-4 Lite

HIGHLIGHTS

Core is compliant to ANSI/VITA 1.0-1994
VME Slave IP provides a bus bridge between VME and AXI interfaces
Supports A32, A16 and A8 addressing modes with D16 data

iWave is an embedded systems engineering and solutions company, designing solutions for the Industrial, Medical, Automotive and Avionics vertical markets, and building on our core competency of embedded expertise since 1999. Read More…

mktg@iwavesystems.com

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VME Slave IP Core (VME to AXI Bridge)

VME Slave IP Core (VME to AXI Bridge)

SPECIFICATION

HIGHLIGHTS

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80186XL Processor

8259A ICU

NAND Flash Controller

Video Scaler

SD Memory Slave Controller

SATA 3.0 Bridge Controller

SDIO Slave Controller

SATA Host Controller

8530 Multi-Protocol Controller

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8237 DMA

ARINC 818-3 IP Core

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