• ZU7/ZU5/ZU4 – Zynq Ultrascale+ MPSoC
  • Processing System (PS)
    • Quad/Dual Arm Cortex-A53 @1.5GHz, Dual Cortex-R5 @600MHz
    • H.264/H.265 Video Encoder/Decoder (VCU)
    • Arm Mali-400MP2 GPU @677MHz
  • Programming Logic (PL)
    • Up to 504K Logic cells & 230K LUTs
    • PL GTH High Speed Transceivers x 16 @16.3 Gbps
• 64bit, 4GB DDR4 RAM with ECC for PS (Upgradable upto 8GB)
• 16bit, 2GB DDR4 RAM for PL (Upgradable upto 4GB)
• 8GB eMMC Flash (Upgradable)
• RGMII Ethernet PHY Transceiver
• USB2.0 ULPI Transceiver

From PS Block

• PS-GTR High Speed Transceivers (upto 6Gbps) x 2
• Gigabit Ethernet x 1 (through On-SOM Gigabit Ethernet PHY)
• USB2.0 OTG x 1 (through On-SOM USB2.0 transceiver)
• RGMII Interface or ULPI Interface x 1
• SD (4bit) x 1
• SPI x 1
• CAN x 2
• Debug UART x 1
• Data UART x 1
• I2C x 2
• PS JTAG

From PL Block

• PL-GTH High Speed Transceivers (upto 16.3Gbps) x 16
• PL IOs – 142 IOs

• • HP Bank IOs – Up to 48 LVDS IOs/96 Single ended (SE)
  • HD Bank IOs – Up to 23 LVDS IOs/46 Single ended (SE)
  • GC Global Clock Input pins – Up to 15 LVDS/SE
  • ADC Input pins – Up to 16 Differential/Single Ended