Processing System (PS)

• Quad/Dual Arm Cortex-A53 at 1.2GHz, Dual Cortex-R5 at 500MHz
• Arm Mali-400MP2 GPU @600MHz

Programming Logic (PL)

• Up to 1143K Logic cells and 522K LUTs
• PL GTY High Speed Transceivers x16 at 28.2Gb/s
• PL GTH High Speed Transceivers x32 at 16.3Gb/s

• 64bit, 4GB DDR4 RAM for PS with ECC
• 64bit, Dual 4GB DDR4 RAM for PL
• 32GB eMMC Flash (Expandable up to 128GB)
• 256MB QSPI
• 2Kb EEPROM

From PS Block

• PS GTR Transceiver Lanes x 2 (Up to 6.0Gb/s)
• Gigabit Ethernet x 1 Port (through On-SOM Gigabit Ethernet PHY)
• SD (4bit) x 1
• Debug UART and Data UART x 1
• SPI x 1(Optional)
• I2C x 2 Port
• JTAG x 1

• High Speed GTH Transceiver Lanes x 4 (Up to 12.5Gbps)
• HD Bank IOs – Up to 48 LVDS/96 Single Ended IO’s
• ADC Input pins – Up to 32 Differential/Single Ended HP Banks