Requirement Analysis & Strategizing best market solution Architecture blue-print using State-of-Art Design Methodologies Implementation & Optimization for Area, Power, Timing & Resources Simulation, Integration and Testing RTL Coding: VHDL, Verilog & System Verilog
ハードウェア - ソフトウェア共同デザイン
Embedded Software Development for SoCs with Soft & Hard IP Cores Complete Software Development Life Cycle (BSP, Driver, APIs, Application) Algorithm Development in FPGAs using High-Level Synthesis – HLS Tools Validation of whole package with in-house platforms viz. SOMs & EVKs
ASICプロトタイピング
Complete Life Cycle of a Chipset Test Specification Capture, Platform Identification, RTL Porting Code Coverage, Lint & CDC Checks Pre-Silicon & Post Silicon Validation, Characterization
AIとML
Low Latency, High Performance, Better Accuracy Running multiple CNNs simultaneously Various CNNs scalable from Edge to Cloud Frameworks: Caffe, TensorFlow, MX Net, Darknet
高速バス＆トランシーバー・ソリューション
Maximum Performance, Low-Latency, Peak Bandwidth up to 25Gbps/ lane Backplane, Board to Board, Mezzanine Card over Copper or Optical Medium Protocol: ARINC818, sRIO, Aurora, PCIe, SATA, JESD204, USB, sFPDP, 10/25/40/100Gb Memory: DDR 4/5, QDR, RLDRAM
画像・映像処理
In-depth experience in working with Image & Video Processing like Chroma Resampler, De-Interlacer, Color Space Conversion, Alpha Blender, Mixer, Scalar, Color Correction & Enhancement, etc., Analog Video: STANAGRGB, CVBS, VGA, Composite Digital Video: HDMI, SDI, Display Port, DVI, ARINC818
