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SD / SDIO / MMC Host Controller



iW-SD Controller interfaces SD / MMC / SDIO card to any processor with a generic interface. The interface towards the SD card is realized by the SD protocol implemented in the controller.

SD / SDIO / MMC Host Controller (FPGA IP Cores)

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  • SD / SDIO / MMC Host Controller (FPGA IP Cores)
  • Compliant with SD specification version 3.0, eMMC specification version 4.41
  • Controller provides a simple slave interface for control & status access and master interface for DMA data transfer
  • Compliant with SD Host Controller Standard Specification Version 3.0
  • Compliant with SD Physical Layer Specification Version 3.0
  • Compliant with SDIO Specification 3.0
  • Compliant with eMMC Specification Version 4.41
  • Supports 1-bit,4-bit SD/eMMC modes and 8-bit eMMC modes
  • Supports SD Card Detection input pin
  • Supports SD Card Write Protection input pin
  • Supports programmable clock frequency generation to the SD/eMMC card
  • Supports Interrupt and ADMA2 transfer mode of operation
  • Individual 2Kbyte data buffer for read and write
  • Cyclic Redundancy Check (CRC) for command and data
  • Supports timeout monitoring for response, data, CRC token & busy
  • Supports a maximum block length of 2K-byte
  • Supports both single block and multi block data transfer.
  • Supports power ON/OFF control to SD/eMMC card
  • supports Default speed, High speed including SDR12, SDR25, DDR50, SDR50 and SDR104
  • Handheld devices and consumer electronics
  • SOC Integration with processor, where the processor in the platform doesn’t support SD/ SDIO/ MMC interface

Please contact mktg@iwavesystems.com

  • Design Document
  • Verilog RTL or Netlist Source code
  • Test Bench
  • IP User Guide


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