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SD Host Controller 3.0 FPGA IP Core by iWave

iWave offers SD Host Controller IP Core, which enables an FPGA / ASIC to access an SD card through its I/O pins. It is compliant with SD Host Controller Standard Specification Version 3.0. This simplifies host system and driver designs by using a standardized implementation that reduces product development time. It defines a standard register set to control SD memory card. It supports Ultra High Speed-I(UHS-I) mode with maximum data rate upto 104MBPS. The iWave SD Host Controller IP Core also provides a sophisticated Advanced direct memory access(ADMA2) function to achieve high-performance data transfers between SD standard host systems and memory cards. Largely because of hardware control, SD transfers data without having to rely on the CPU specifications.


The Host Controller has two interfaces:The System side interface and the SD Bus interface. The System side interface is AXI4 interface so that The IP Core can be easily integrated   with the rest of the system.


  • Compliant with SD Host Controller Standard Specification Version 3.0
  • Compliant with SD Physical Layer Specification Version 3.0
  • Supports 1-bit,4-bit SD modes
  • Supports SD Card Detection input pin
  • Supports SD Card Write Protection input pin
  • Supports programmable clock frequency generation to the SD card
  • Supports Interrupt and ADMA2 transfer mode of operation
  • Individual 2Kbyte data buffer for read and write
  • Cyclic Redundancy Check (CRC) for command and data
  • Supports timeout monitoring for response, data, CRC token & busy
  • Supports a maximum block length of 2Kbyte
  • Supports both single block and multi block data transfer
  • Supports 32-bit AXI4 memory mapped interface towards host processor
  • Supports 32-bit AXI4 Lite interface towards SD host Controller
  • UHS-I Mode Support
    • Tuning Support for SDR50 and SDR104 mode
    • 3.3V to 1.8V Switch support
    • Support SDR12, SDR25, SDR50, DDR 50 and SDR104 mode
    • Maximum Data rate upto 104MBPS

IP Validation: The IP Validation of SDR12, SDR25, SDR50, DDR 50 and SDR104 mode is performed on Xilinx ZED board. The setup used is as shown below.



iWave will provide reference designs and SD Linux Platform Driver for testing this IP.

Following are the IP Deliverables :

  • Design Document
  • RTL code or Device specific Net list
  • IP User guide
  • iWave SD Linux Platform Driver

To see the entire range of FPGA IP cores offered by iWave Click Here.

For further information or enquiries please write to [email protected] or contact our Regional Partners.

-Anil M

Senior Engineer

iWave Systems Technologies Pvt. Ltd.