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8259A Interrupt Controller



8259A Interrupt Controller is designed to transfer the interrupt with highest priority to the CPU, along with interrupt address information.

8259A Interrupt Controller (FPGA IP Cores)

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  • 8259A Interrupt Controller (FPGA IP Cores)
  • Compatible with 8259A and uPD71059
  • Two modes of operation make the controller compatible with 8080/85 and 8086/88/286 microprocessors
  • Microcomputer system with I/O devices are serviced with efficient manner by using iW-8259A interrupt controller
  • Eight interrupt request input per chip
  • Up to 64 interrupt request inputs per system
  • Edge or level triggered interrupt request inputs
  • Individually maskable interrupt requests
  • Programmable interrupt request priority orders
  • Polling operation capability
  • Extended mode with cascade connection of external interrupts
  • Supports Slave mode in extended mode


  • Core is designed to use with industry standard microprocessors such as 80286, 8086/8088, 8080/85.
  • Design Document
  • Verilog RTL or Netlist Source code
  • Test Bench
  • IP User Guide

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