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Interface Cores

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Serial FPDP (sFPDP)

Serial FPDP (sFPDP)

sFPDP IP Core is based on ANSI/VITA 17.1-2003 Standards. This IP core provides a relatively simple protocol using maximum available data throughput with a minimum protocol for point-to-point data links. sFPDP links support a wide range of physical interfaces with the most common option being 2.5 gigabits per second multimode fiber.

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SDIO to UART Controller

SDIO to UART Controller (FPGA IP Cores)

iW-SDIO to UART bridge is a IP core which converts SDIO slave to UART bus interface.

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PCI Controller

PCI Controller (FPGA IP Cores)

PCI Controller provides an interface between the PCI bus and user interface. PCI core interface is processor independent, enabling an efficient transition to future processor generations and use with multiple processors.

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PCIe to UART Bridge

PCIe to UART Bridge (FPGA IP Cores)

PCIe to UART bride is a IP core which converts PCIe to UART bus interface

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PCIe-ISA Bridge

PCIe-ISA Bridge (FPGA IP Cores)

PCIe to ISA bride is a IP core which converts PCIe to ISA master bus interface.

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PCIe to SD/MMC Bridge

PCIe to SD/MMC Bridge (FPGA IP Cores)

iW-PCIe to SD/MMC Bridge is the IP core which converts the PCIe to SD or MMC bus interface

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DMA Core for PCIe Hard IP

DMA Core for PCIe Hard IP

iWave provides the user application for PCI-e target bridge to access the control & status registers of custom logic and data transfers to custom logic. In addition multi-channel scatter gather DMA core provides the hardware assisted high speed data transfers between the PCI-e and custom logic. This IP core simplifies the integration of PCI-e hard macro controller with custom logic.

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VME Slave IP Core (VME to AXI Bus Bridge)

VME Slave IP Core

The ANSI/VITA 1.0-1994 or VME64 specification establishes a framework for 8-, 16-, and 32-bit parallel bus computer architectures that can implement single and multiprocessor systems. The VMEbus specification defines an interfacing system used to interconnect microprocessors, data storage, and peripheral control devices in a closely coupled hardware configuration.

iWave’s IP is compliant to ANSI/VITA1.0-1994 and implements the slave configuration of VMEbus data transfer layer consisting of the Data Transfer Bus and the Priority Interrupt Bus modules. This IP can be considered as a VME to AXI bus bridge and can be implemented in any FPGA having interface to a VME Bus Interface.

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