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FPGA IP Cores

iWave is a leading FPGA design house with a wide range of FPGA IP Cores. The Design House caters to multiple customers across the globe by customizing and integrating the IPs, thereby reducing the effort, time to market and cost factors. iWave has a bundle of well tested and proven FPGA IP cores, which include Intel 80186 compatible Processor & peripheral cores, bus interfaces cores, video/multimedia cores and storage cores. All the FPGA IP cores provide standard and simple user interface for ease of use.

All the IP cores are optimized for leading FPGA’s and delivered with full documentation, VHDL/Verilog synthesizable RTL or optimized netlist for leading FPGA’s, VHDL/Verilog/SystemVerilog testbench for simulation and example design with IP user manual for system integration.

iWave upgrades all IP portfolios on regular basis to cater the market requirements. In addition to IP cores, we offer FPGA Design Services and Board development for complete realization of solutions. For any more information please contact [email protected]


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ARINC 818-2 IP Core

ARINC 818-2 IP Core

iWave's ARINC IP core is ARINC 818–compliant, which can be implemented on any transceiver based FPGA. It can be used for both transmit-and-receive applications. This core has flexible user interface, allowing for various video parameter configuration. This IP core supports Line Synchronous Mode.

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80186EC Processor

80186EC Processor

The 80186EC is a powerful 16-bit microprocessor core, executes instruction list compatible with 80186EC microprocessor. The 80186EC core has a broad set of integrated peripherals, which helps reduce system development time and cost and is compatible with wide range of compilers and debuggers. The design along with multiple peripherals can be fit into single FPGA.

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SDIO to UART Controller

SDIO to UART Controller (FPGA IP Cores)

iW-SDIO to UART bridge is a IP core which converts SDIO slave to UART bus interface.

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SATA Host Controller

sata host controller ip

The SATA Host Core is available for integration into host FPGA designs to provide an industry- compliant SATA 1.5-Gbps and SATA 3.0-Gbps interface. Serial ATA (SATA) are computer bus standards that have the primary function of transferring data (directly or otherwise) between the FPGA and mass storage devices such as hard disk.

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Serial FPDP (sFPDP)

Serial FPDP (sFPDP)

sFPDP IP Core is based on ANSI/VITA 17.1-2003 Standards. This IP core provides a relatively simple protocol using maximum available data throughput with a minimum protocol for point-to-point data links. sFPDP links support a wide range of physical interfaces with the most common option being 2.5 gigabits per second multimode fiber.

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SD / SDIO Host Controller 3.0

SD / SDIO Host Controller FPGA IP Core

iW-SDXC Host controller is compatible with the SD Physical Layer specification V3.0. The core supports 32 bit AHB LITE Host interface working at SOC interface frequency. The Host interface is compatible with the standard register set for the host controller as per SD host controller specification Version 3.0.

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Video Encoder Interface

Video Encoder Interface

Video Encoder Interface core accepts unformatted video data (without blanking/synchronization information) in 10-bit Y’CbCr 4:2:2 format and outputs 10-bit synchronized video in conformance with BT.601/656 recommendation to a video encoder.

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Video Decoder Interface

Video Decoder Interface

Video Decoder Interface core accepts BT601/656 video frames (digitized NTSC/PAL) in 10-bit Y'CbCr 4:2:2 format from a video decoder of an analog camera and outputs 16-bit video data in the same format in a continuous stream without blanking and synchronization information.

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