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PCIe to UART Bridge



PCIe to UART bride is a IP core which converts PCIe to UART bus interface

PCIe to UART Bridge (FPGA IP Cores)

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  • PCIe to UART Bridge (FPGA IP Cores)
  • Quick Migration to 16650 UART
  • The following are the main features of the PCIe to UART Controller:

    • System Interface
    • 100MHz external reference clock for synchronous clocking of PCI express Interface
    • Supports interface to external active low reset signal
    • PCI Express Interface
    • Compliant with the PCI Express base specification v1.1
    • Lane width supported x1
  • Link speed supported 2.5 Gbps
  • User interface width supported 32-bit
  • PCI Express Application Interface
  • Target only support
  • Memory BAR0 supported for UART controller.
  • UART Interface
  • The UART bridge uses IO mapped interface
  • Full duplex asynchronous communication
  • Baud rate of 115200 with a single odd parity, stop & start bit
  • Supports transmit & receive synchronous FIFO of size 16 byte depth
  • Used in POS
  • Design Document
  • Verilog RTL or Netlist Source code
  • Test Bench
  • IP User Guide


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