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NAND Flash Controller



NAND Host Controller provides an easy interface to access NAND Flash Memory devices. It handles all set of commands, address and data sequence

NAND Flash Controller (FPGA IP Cores)

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  • NAND Flash Controller (FPGA IP Cores)
  • Core is compliant with Open ONFI 1.0 standard
  • Controller supports rich set of NAND commands
  • Simple streaming interface towards user logic for data read and write

  • Commands supported towards NAND Flash Memory:

    • Read
    • Read for Copy Back
    • Reset
    • Page Program,
    • Copy-Back Program,
    • Block Erase,
    • Random Data Input,
    • Random Data Output and Read Status
  • ECC Logic: Hamming code used to correct 1-bit error and detect 2-bit errors
  • Commands supported from user: Block Erase, Read, Program and Copy-Back Program
  • Supports timeout mechanism for all NAND commands and operations
  • 2K-byte buffer for write data
  • 2K-byte buffer for read data
  • Identify factory defined invalid blocks
  • Consumer Electronic
  • Commercial/Industrial
  • Medical and Computing
  • Design Document
  • Verilog RTL or Netlist Source code
  • Test Bench
  • IP User Guide


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