• Quick migration of 80188EB based designs to an FPGA platform
• Replacement for 80188EB processor and ASICs

• Multiplexed 20-bit address and 8-bit data bus
• 1M-byte memory space divided into 4 segments
• 64K-byte IO space
• Non Maskable Interrupt support
• Arithmetic-Logic Unit
• 8,16,32-bit arithmetic operations
• 8,16-bit logical operations
• Boolean manipulations
• 16 x 16 bit multiplication (signed or unsigned)
• 32/16-bit division (signed or unsigned)
• CPU On-Chip Peripherals
• Programmable Timer / Counter Unit
• Three programmable independent 16-bit timers
• TOUT0 to TOUT1 pin outputs
• TIN0 & TIN1 used either as clock or control signals
• Timer-2 can be used to clock other two timers
• Internal / external input clock selectable
• Serial Communications Unit
• RS-232-C protocol support (on-chip CTS_N, SINT_N pins)
• Both synchronous and asynchronous modes are supported
• Two independent identical channels
• Full duplex operation in asynchronous mode

• Half-duplex operation in synchronous mode
• Programmable seven, eight or nine data bits in asynchronous mode
• Independent baud rate generator
• Double-buffered transmit and receive
• Clear-to-Send feature for transmission
• Break character transmission and detection
• Programmable even, odd or no parity
• Detects both framing and overrun errors
• Supports interrupt on transmit and receive
• Interrupt Controller Unit
• Edge trigger / level trigger selectable
• Individually maskable interrupt requests
• Programmable interrupt request priority orders
• Supports Cascading (Only INTP0 and INTP1) and polling mode
• 5 external interrupt request inputs (INTP0 to INTP4)
• 2 internal interrupt input pins (SCU and TCU)
• Chip Select Unit
• Ten programmable chip-select outputs
• Programmable start and stop addresses
• Memory or I/O bus cycle decoder
• Programmable wait-state generator
• Provision to disable a chip-select
• Provision to override bus ready
• Clock Generator
• Two 8-bit multiplexed Input/output Ports

• Typical processor applications such as industrial, Automotive, Medical etc.
• Legacy platforms with obsolete components can be converted to new FPGA board

Please contact [email protected]

• Design Document
• Verilog RTL or Netlist Source code
• Test Bench
• IP User Guide