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Documents
Intel Evaluation Kit
Mircochip Evaluation Kit
SPECIFICATION
- Compliant with ANSI/VITA 17.1-2015 Serial FPDP standard
- Supported link speeds
- Up to 10Gbuad
- Data Frames supported
- Unframed Data
- Single Frame Data
- Fixed Size Repeating Frame Data
- Dynamic Size Repeating Frame Data
- System Configurations supported
- Basic System Flow Control
- Bi-directional Data Flow
Copy Mode
Copy/Loop Mode
- Unidirectional support
Optional flow control
CRC
Host-Bus interface
Parallel FPDP
Configurable parameters Transmit FIFO depth
Receive FIFO depth
Transmit FIFO watermark to assert SUSPEND output
Transmit FIFO watermark for TX FIFO Overflow signal generation
Receive FIFO watermark for STOP/GO signal generation
HIGHLIGHTS
- Serial Front Panel Data Port (sFPDP) IP core for FPGA is based on the ANSI/VITA 17.1-2015 standard
- The Serial FPDP standard supports Up to 10Gbuad link speed.
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