iWave's SDRAM Controller

Core Benifits

Eases SOC integration
Configurable for ease of use

Core Applications

Single Data Rate SDRAM devices

Deliverables

Technical Specification
RTL Verilog Synthesisable Code
Comprehensive Test Environment
Technical Support and Maintenance

iW-SDRAM Controller

Brochure

iW-SDRAM Controller provides a simplified interface to the industry standard SDR SDRAM memory. It consists of address multiplexer, refresh timer, control signal generator and mode register implementation.

iW-SDRAM Controller

Features

SDRAM burst length of 1,2,4, 8 and full page mode
CAS latency of 2, 3 or 4
16 bit programmable refresh counter used for auto refresh
Supports the followingcommands:NOP, PRECHARGE, AUTO_REFRESH, LOAD_MR, READ, WRITE and BURST_STOP
Data Mask lines are supported for write operations
Operates at 133 MHz of frequency
Fully synchronous, positive clock edge design
Synthesisable RTL code
Available in Verilog version

For further details, contact mktg@iwavesystems.com