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SD Memory Slave Controller FPGA IP

iW-SD memory slave controller IP is compliant with SD Physical Specification Version 2.0 with both 1-bit and 4-bit mode. The IP supports both high speed and default operation for standard & high capacity memory. The IP abides all the mandatory commands defined in the SD specification. The data transfer supports a maximum block length of 512 bytes. It hosts all mandatory slave register set and header file can be used to configure the CID Register fields. SD memory slave controller limits to SD memory-only implementation and does not support the SPI mode and combo card features.

SD Memory Slave Controller FPGA IP


SD memory slave controller handles SD bus protocol on the card interface and provides simplified general purpose interface to user logic. It receives the commands through the SD interface and generates the corresponding responses locally and forwards exclusively the data transfer requests to user interface.

Application Diagram

FPGA SD Memory Slave Controller IP

iWave provides the SD memory slave reference design which can be used to validate the functionality of the IP. This design contains user application of 2KB interfacing the IP. The basic read/write operation can be tested using this reference design. The functionality and the attributes supported by the IP can be demonstrated using the iWave’s reference design on the demo board which has Actel Proasic3 (A3P250-PQFP 208) FPGA with SD interface. The IP has a wide variety of applications in the field of automotive, security and wired and wireless communication with wide range of target platforms such as smart phones, PDAs, etc.




SD Memor Slave Demo Board

iW- SD memory slave controller has been implemented in various applications globally by different customers. One of such applications is described in the below figure:

FPGA SD Memory Slave Controller IP

SD memory Slave IP Application

As depicted in the figure, the SD memory slave controller acts as the bridge between the SD host and microcontroller. The SD host communicates with the IP on one side and with the microcontroller via customized asynchronous interface on the other side. On the write cycle, the data is passed from the SD host to the microcontroller, which in-turn writes to the flash. In the read operation, data from the flash will be read by the microcontroller and passed to the SD host. This design has been tested and proven in Linux and Android operating systems.

For further information or enquiries please write to mktg@iwavesystems.com or contact our Regional Partners

Deepak B. – Senior Engineer (Hardware)
iWave Systems Technologies Pvt. Ltd.