iWave's ARINC IP core is ARINC 818–compliant, which can be implemented on any transceiver based FPGA. It can be used for both transmit-and-receive applications. This core has flexible user interface, allowing for various video parameter configuration. This IP core supports Line Synchronous Mode.
LCD/HDMI Video output Interface supports various display modes and programmable display sizes. This core formats the incoming active video input into clocked video output by generating horizontal and vertical synchronization information and inserting horizontal and vertical blanking.
Video Encoder Interface core accepts unformatted video data (without blanking/synchronization information) in 10-bit Y’CbCr 4:2:2 format and outputs 10-bit synchronized video in conformance with BT.601/656 recommendation to a video encoder.
Video De-Interlacer converts the interlaced video signals into non-interlaced signals. This core separates the intermeshed odd and even fields of the NTSC/PAL frames output by the video decoder, into a combined, sequential de-interlaced frame, in order to display on LCD.