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SD / SDIO Host Controller 3.0


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Overview

iW-SDXC Host controller is compatible with the SD Physical Layer specification V3.0. The core supports 32 bit AHB LITE Host interface working at SOC interface frequency. The Host interface is compatible with the standard register set for the host controller as per SD host controller specification Version 3.0.

SD / SDIO Host Controller FPGA IP Core

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  • SD / SDIO Host Controller FPGA IP Core
  • Controller supports standard register set for the host controller
  • Core offers UHS-I mode of operation
  • Compliant with SD Host Controller Standard Specification Version 3.0
  • Compliant with SD Physical Layer Specification Version 3.0
  • Supports 1-bit,4-bit SD modes
  • Supports SD Card Detection input pin
  • Supports SD Card Write Protection input pin
  • Supports following UHS –I modes of operations:
    • SDR12 – SDR up to 25MHz 1.8V signaling
    • SDR25 – SDR up to 50MHz 1.8V signaling
    • SDR50 – SDR up to 100MHz 1.8V signaling
    • DDR50 – DDR up to 50MHz 1.8V signaling
    • SDR104 – SDR up to 208MHz 1.8V signaling

  • Supports programmable clock frequency generation to the SD card
  • Supports Interrupt and ADMA2 transfer mode of operation
  • Individual 2Kbyte data buffer for read and write
  • Cyclic Redundancy Check (CRC) for command and data
  • Supports timeout monitoring for response, data, CRC token & busy
  • Supports a maximum block length of 2Kbyte
  • Supports both single block and multi block data transfer
  • Supports 32-bit AXI4 memory mapped interface towards host processor
  • Supports 32-bit AXI4 lite interface towards SD host Controller
  • Support tuning block and support 1.8 voltage switching
  • Handheld devices and consumer electronics
  • SOC Integration with processor, where the processor in the platform doesn’t support SDXC interface
  • Design Document
  • Verilog RTL or Netlist Source code
  • Test Bench
  • IP User Guide

 

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