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sFPDP IP Core is based on ANSI/VITA 17.1-2003 Standards. This IP core provides a relatively simple protocol using maximum available data throughput with a minimum protocol for point-to-point data links. sFPDP links support a wide range of physical interfaces with the most common option being 2.5 gigabits per second multimode fiber.
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Serial Front Panel Data Port (sFPDP) IP core for FPGA is based on the ANSI/VITA 17.1-2003 standard. The Serial FPDP standard supports three data rates: 1.0625 Gbaud, 2.125 Gbaud, and 2.500 Gbaud.
Compliant with ANSI/VITA 17.1-2003 Serial FPDP standard
Supported link speeds
Data Frames supported
Dynamic Size Repeating Frame Data
System Configurations supported
Configurable parametersTransmit FIFO depth
Transmit FIFO watermark for TX FIFO Overflow signal generation
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