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PCIe-ISA Bridge


Rs0.00

Overview

PCIe to ISA bride is a IP core which converts PCIe to ISA master bus interface.

PCIe-ISA Bridge (FPGA IP Cores)

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  • PCIe-ISA Bridge (FPGA IP Cores)
  • Quick Migration to PC104 bus
  • Quick Migration to LPC bus
  • The following are the main features of the PCIe to ISA Bus Controller:
    • System Interface
    • 100MHz external reference clock for synchronous clocking of PCI express Interface
    • Supports interface to external active low reset signal
    • PCI Express Interface
    • Compliant with the PCI Express base specification v1.1
    • Lane width supported x1
    • Link speed supported 2.5 Gbps
    • User interface width supported 32-bit
    • PCI Express Application Interface
  • Target only support
  • I/O BAR0 supported for ISA I/O bus access
  • Memory BAR1 supported for ISA memory bus access.
  • ISA Master Interface
    • The ISA Bridge implements a 16-bit data interface
    • Supports Bus clock of 8 MHz for ISA interface
    • Supports a 20-bit system address lines tristate, which can be latched on to the falling edge of bus address latch enable signal
    • Supports latchable address lines, these unlatched address signals give the system up to 16 MB of address ability
  • Used industrial and embedded application
  • Used in computer mother board
  • Design Document
  • Verilog RTL or Netlist Source code
  • Test Bench
  • IP User Guide

 

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