iW-PCIe to UART Bridge
The iW-PCIe to UART Bridge consists of a single UART controller & a Xilinx endpoint core for PCIe with PHY interface. The PCIe to UART bridge is a 32 bit PCI express interface that fits into a single Spartan3 FPGA
Features
PCIe Interface
- 32 bit PCIe interface with Xilinx endpoint core for PCIe with external PHY hardware.
- The Xilinx endpoint core for PCIe follows PCI express base specification v1.1 layering model
- Endpoint core implements the physical layer, datalink layer, transaction layer & configuration management layer
- Six individually programmable BAR's & expansion ROM BAR
- MSI & INTX emulation.
- Removal of corrupt packets for error detection and recovery
- Compatible with PCI/PCI Express power management functions
- Used in conjunction with NXP PX1011A PCI Express standalone PHY to achieve high transceiver capability
- 2.5 Gbps line speed, Automatic clock and data recovery, 8b/10b encode and decode
- Maximum transaction payload of up to 512 bytes
UART Interface
- RS-232-C protocol support
- Asynchronous communication only
- Serial interrupt support
- Clock rates of baud rate x 16 or baud rate x 64
- Character length of 7 or 8 bits
- 1 or 2 Stop bits
- Break transmission
- Automatic break detection
- Full duplex double buffer system
- Parity addition/checking
- Error detection for parity, overrun and framing
For further details, contact mktg@iwavesystems.com
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