iW-PCIe to ISA Bridge
The iW-PCIe to ISA Bridge consists of a single ISA bus controller & a Xilinx endpoint core for PCIe with PHY interface. The PCIe bridge is a 32 bit PCI express interface that fits into a single Spartan3 FPGA.
Features
PCIe Interface
- 32 bit PCIe interface with Xilinx endpoint core for PCIe with external PHY hardware.
- The Xilinx endpoint core for PCIe follows PCI express base specification v1.1 layering model
- Endpoint core implements the physical layer, datalink layer, transaction layer & configuration management layer
- Six individually programmable BAR's & expansion ROM BAR
- MSI & INTX emulation.
- Removal of corrupt packets for error detection and recovery
- Compatible with PCI/PCI Express power management functions
- Used in conjunction with NXP PX1011A PCI Express standalone PHY to achieve high transceiver capability
- 2.5 Gbps line speed, Automatic clock and data recovery, 8b/10b encode and decode
- Maximum transaction payload of up to 512 bytes
ISA Interface
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The ISA bridge implements a 16 bit data interface
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Bus clock of 6 to 8Mhz for ISA interface
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20 bit system address lines tristate which can be latched on to the falling edge of bus address latch enable signal
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Latchable address lines, these unlatched address signals give the system up to 16 MB of address ability
For further details, contact mktg@iwavesystems.com
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