Deliverables:

  • Design document
  • RTL Verilog synthesizable code
  • Verification environment
  • Detailed user guide

 

 

iW-PCI Controller

Brochure

iW-PCI Controller provides an interface between the PCI bus and user interface. The core consists of PCI master block, PCI target block, Parity generator/Checker and etc.

iW-Video DeInterlacer

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Features

  • 64-bit, 66MHz PCI interface.
  • Separate initiator and target functional blocks.
  • Supported initiator commands and functions:
    • Configuration read / write.
    • Memory read / write, memory read multiple, memory read line.
    • I/O read / write.
    • Interrupt acknowledge, special cycles.
    • Parity generation, parity error detection.
    • Master abort.
  • Supported Target commands and functions:
    • Type 0 configuration space header.
    • Up to six base address registers.
    • Memory read / write, memory read multiple, memory read line.
    • I/O read / write.
    • Medium speed DEVSEL timing.
    • Interrupt acknowledge.
    • Parity generation, parity error detection.
    • Target abort, target retry, target disconnect.
  • Supports a very generic user interface.

For further details, contact mktg@iwavesystems.com

 
 

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