iWave's PCI Host Bridge

Core Benefits

Embedded applications in Networking and Telecommunication Systems
High speed, high performance peripheral applications

Deliverables

Design document
RTL Verilog synthesizable code
Verification environment
Detailed user guide

iW- PCI Host Bridge

Brochure

iW- PCI-Host Bridge provides an interface between the PCI bus and a generic local bus, which can be customizable to any bus architecture. It consists of two independent units, one handling transactions originating on the PCI bus, the other one handling transactions originating on the local bus.

Click here to view large image

Features

32 / 64 - bit, 33 / 66 MHz PCI interface *
Compliant with PCI specification, R2.2
Seperated initiator and target functional blocks
Supported initiator commands and functions :

Memory Read / Write
Memory Read Multiple (MRM)
Memory Read Line (MRL)
I / O Read, I / O Write
Configuration Read / Write
Bus Parking
Interrupt Acknowledge
Full Command / Status registers
Configurable on-chip FIFO

* Available as optimized 32 - bit and 64 - bithost host bridge cores

Supported target commands and functions :

Type 0 Configuration Space Header
Parity Generation (PAR)
Parity Error Detection (PERR# and SERR#)
Memory read / Write
Memory Read Multiple (MRM)
Memory Read Line (MRL)
I / O Read, I / O Write
Configuration Read / Write
Target Abort / Retry / Disconnect
Fast Back-to-Back capable target response

Synthesisable RTL code
Fully synchronous, posedge design
Available in Verilog version

For further details, contact mktg@iwavesystems.com