Deliverables:

  • Design document
  • RTL Verilog synthesizable code
  • Verification environment
  • Detailed user guide

 

 

 

 

iW-Multibus Interface

Technical Specification

 

iW-Multibus II Interface controller core is used to interface the external interface signals of the host processor with the Multibus interface. It also contains the controller logic to generate the control signals towards the dual port RAM.

Key Features

  • Multi bus interface at 10MHz.
  • Generic 16-bit CPU Interface
  • Interrupt Generation.

For further details, contact mktg@iwavesystems.com

 
 

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