Deliverables:

  • Design document
  • RTL Verilog synthesizable code
  • Verification environment
  • Detailed user guide

 

 

 

 

iW-LPC-SPI Bridge

iW-LPC to SPI bridge provides an interface between LPC bus and SPI bus.The core consists of SPI master controller which facilitates to access SPI devices.
Technical Specification Resource Summary for Xilinx Resource Summary for Actel  

Features

  • LPC Bus interface:
    • Compliant with Intel’s LPC interface specification Revision 1.1.
    • Supports LPC bus cycle types : Memory, I/O, and Firmware Memory
    • Support for LPC slave interface.
    • Synchronous 33MHz bus clock cycles.
    • Multiplexed Command, Address and Data Bus
    • Supports 8-bit transfer size.
  • SPI Bus interface:
    • Supports SPI master mode
    • Supports Full duplex mode .
    • Supports one SPI slave select line
    • Serial clock with programmable polarity and phase
    • Supports Interrupt generation

For further details, contact mktg@iwavesystems.com

 
 

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