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Features
- Eight interrupt request input per chip
- Up to 64 interrupt request inputs per system
- Edge or level triggered interrupt request inputs
- Individually maskable interrupt requests
- Programmable interrupt request priority orders
- Polling operation capability
- Extended mode with cascade connection of external interrupts
- Supports Slave mode in extended mode
Deliverables:
- Design document
- RTL Verilog synthesizable code
- Verification environment
- Detailed user guide
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iW-Interrupt Controller
iW-Interrupt Controller is designed to transfer the interrupt with highest priority to the CPU, along with interrupt address information.
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Core Benefits
- Can be used to assign priority levels to interrupt outputs
- Allows cascading of multiple interrupts
For further details, contact mktg@iwavesystems.com |
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