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Core Benifits
- User interface is generic and can be easily modified for any other processors.
Enhancements
- Programmable burst length of 4 & 8
- Programmable CAS latency of 2.5 & 3
- Support to read/write DDR SDRAM configuration registers.
Deliverables
- Design document
- RTL Verilog synthesizable code
- Verification environment
- Detailed user guide
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iW-DDR SDRAM Controller
iW-DDR SDRAM Controller provides the user with a simplified interface to industry standard DDR SDRAM memory devices
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Features
- Operates at 100 MHz(200 DDR)
- Interface to JEDEC standard DDR SDRAM
- Programmable DDR SDRAM data width
- Supports upto 4 external memory banks
- Uses DCM to generate all internal clocks
- Fixed CAS latency of 2
- Fixed RAS to CAS delay of 2
- Single access and random read/write access to achieve high bandwidth
- A burst of 512 data access with random read/write mode
- Manual precharge after cycle terminates
- Utilizes FPGAIOB architecture to provide clock, data and DQS to the DDR SDRAM with minimal skew
- Interface with DDR SDRAM using SSTL2 I/Os
- Complete synchronous implementation
- Bus interface to ARM9 readily available
- Available in Verilog version
For further details, contact mktg@iwavesystems.com |
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