iWave's DDR2 Controller

Core Benifits

Reliable and easy-to-integrate core
Configurable to different FPGAs.

Core Applications

All kind of video/image processing applications that uses DDR2 memory

Deliverables

Design document
RTL Verilog synthesizable code
Verification environment
Detailed user guide

iW-DDR2 Controller

Brochure

iW-DDR2 Controller core performs initialization of the DDR2 memory and provides necessary commands for a memory read or memory write access. It acts as an interface between the memory device and DMA Interface.

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Features

Interface to DDR2 SDRAM of configuration 16Mx32-bit
Supports 4-memory banks
CAS latency supported is 5
Sequential burst of 8 data supported
Posted CAS operation supported
Auto Precharge is supported during DDR2 initialization and Manual Precharge after every read/write
On Die Termination of DDR2 device for the data bus, data strobe and data mask are supported

For further details, contact mktg@iwavesystems.com