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Experiencing SLS USB 3.1 Gen2 Device Interface on iWave Arria 10 SOM Board

iWave Systems joining hands with SLS an industry leading IP core company, supporting USB3.1 Gen2 Device IP core on iWave's Arria 10 SOM module. Together with iWave’s Arria 10 SOC development kit and SLS's eUSB3.1 FMC Snap on board, the SLS’s USB3.1 Gen2 Device IP is tested and verified for highest throughput greater than 7Gbps. Avalon interface allows to manage the control transfer using software and provides flexibility, while FIFO interface allows to transfer the data over non-control endpoint ensuring highest throughput.

SLS is one stop shop for all USB requirements and it recently announced Industry's first USB3.1 Gen2 (10Gbps) Device IP core implemented using Intel FPGA's built-in transceiver. Use of FPGA's built-in transceiver as a USB3.1 PHY layer greatly reduces board design space, cost and complexity.

usb3.1-gen2-device-ip-architecture

USB3.1 Gen2 Device IP Architecture

Features:

  • USB 3.1 Specific Features:
    • Supports SuperSpeedPlus (SSP - USB 3.1 Gen 2) mode
    • Supports SuperSpeed (SS - USB3.1 Gen 1) mode
    • Uses Intel Transceiver as a PHY layer and thus eliminates need for external PHY for USB 3.1

  • USB 2.0 Specific Features:
    • Supports High Speed (HS) and Full Speed (FS) modes
    • Provides well known ULPI interface to interact with external USB 2.0 PHY

  • Ease of Use:
    • Ready to use component for Intel’s Qsys
    • Simple FIFO interface to transfer data over non-control endpoint

  • Flexibility:
    • Capable to support up to 31 endpoints (1 default control endpoint, 15 IN endpoints and 15 OUT endpoints)
    • Allows to select number of buffers per endpoint based on the requirement

Performance Results: usb3.0-arria-10-performance-result

Implementation Results:

usb3.0-arria-10-implementation-result

  Features of iWave Arria 10 SOM:

usb3.0-gen2-arria-10-som

  • Arria 10 Devices Supported:
    • SOC: SX270, SX320, SX480, SX570, SX660
    • FPGA: GX270, GX480, GX570, GX660, GX900, GX1150

  • SOM Highlights:
    • ECC RAM support for HPS
    • 24 high speed transceivers @ 17.4Gbps
    • Up to 76LVDS/152SE FPGA
    • 8LVDS/8SE General Purpose Clock outputs
    • 7LVDS/7SE General Purpose Clock inputs
    • 64-Bit DDR4 support for FPGA
    • Variable IO voltage support
    • Industrial grade operation

For more information on USB 3.1 Gen 2 Device Controller, please visit: http://www.slscorp.com/ip-cores/communication/eusb-3-1-gen-2-device-controller-eusb31sf.html

For further information or enquiries please write to mktg@iwavesystems.com or contact our Regional Partners.