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ARINC818-2 IP Core Evaluation Platform

iWave offers ARINC818 FPGA IP core that is compatible with ARINC 818-2 specification. ARINC 818-2, is an industry standard high speed serial protocol, specifically developed for avionics applications. This article provides details of iWave's ARINC818-2 IP core Evaluation. This is a continuation of the previous article "ARINC 818-2 FPGA IP Core"  http://www.iwavesystems.com/arinc-818-2-fpga-ip-core.

Streaming Interface feature of ARINC818-2 IP made easy to integrate this with available FPGA specific streaming IP and use it for different video application. iWave’s ARINC818 IP is tested and validated on Xilinx Kintex 7 FPGA Evaluation kit and Altera Stratix IV GX FPGA development board as per following ICD detail.

  • Link Characteristic: 3.125 Gbps interface.
  • Video Format : The ADVB shall have the following video format:Single video stream (single container)
    • Resolution –1280x1024
    • Scan – Progressive (left to right, starting at top)
    • Frame rate –60 Hz
  • Single video stream (single container) 
  • Object 0 segmented in the first transmitted ADVB frame in each Video frame
  • Object 2 frames
    • Total 2048 (2*1024) ADVB Frames
    • All frames shall contain exactly one half line (1920 ((1280*3)/2) bytes)

ARINC818 IP Evaluation On Altera Stratix IV GX Development Board:

The IP has been tested on Altera Strartix IV GX Development using HSMC DVI Input and Output daughter card and HSMC transceiver daughter card. DVI Input data is streamed to ARINC IP. ARINC IP transmitter data is looped back using SFP and received by ARINC Receiver channel and unframed data displayed on the DVI Output Interface. Refer below block diagram for implementation detail.

 arinc-evaluation-ip-core

Implemenation of ARINC IP on Altera Stratix IV GX Development Board

arinc-evaluation-altera-platform

Validation of ARINC IP on Altera Stratix IV GX Development Board

IP Evaluation On Xilinx Kintex 7 Evaluation Kit:

ARINC IP is integrated with transceiver and Xilinx Video IPs in reference design. Test pattern data is passed to ARINC IP. Transceiver is connected to the ARINC818-2 IP on one side and connected to the SFP module on the other side. The data from the ARINC818-2 IP transmitter will be sent to the SFP module and looped back data received by ARINC receiver and displayed on HDMI port. Below block diagram shows the implementation.

arinc-evaluation

Implementation of ARINC IP on Xilinx Kintex 7 Evaluation Kit

arinc-evaluation-altera-stratix-board

Validation of ARINC IP on Xilinx Kintex 7 Evaluation Kit

There is flexibility to modify the IP as per customer provided ICD (Interface Control document, which defines key parameters like link speed, video resolution, colour format, ancillary data detail and timing details).iWave will modify the IP as per ICD and provide evaluation reference designs for any development kit with SFP, and Video Input and output ports in short period.

 

Videos:

 

For further information or enquiries please write to mktg@iwavesystems.com or contact our Regional Partners.

Preeti Naik – Senior Engineer

iWave Systems Technologies Pvt. Ltd.