Accelerate performance and design productivity with OpenCL on Cyclone V SoC Qseven SOM
The iW-RainboW-G17M-Q7 SOM is based on Altera's Cyclone V SX SoC based Qseven compatible module for the increased system performance requirements. The Dual ARM Cortex A9 core with the FPGA allows greater flexibility for the system designers and helps to lower the system cost and power consumption. The improved logic integration with integrated high speed transceivers and hard memory controllers provides increased bandwidth capacity which is ideal for cost-sensitive high end applications.
Why iW-RainboW-G17M-Q7 has CPU+FPGA in SoC?
Market dynamics in almost all end markets are driving the industry toward programmability in silicon. The convergence of technology and the value that programmability offers customers are driving the broad adoption of FPGAs. FPGAs are widely used in telecommunications, networking, computer, storage, industrial, automotive, and defense applications.
Programmability, combined with the latest hard and soft IP and other technologies, enables customers to get the best balance of performance in their systems.
iW-RainboW-G17M-Q7 meets the Treands towards FPGA:
The demand for increased heterogeneity in computing systems is partially due to the need for high-performance, highly reactive systems that interact with other environments. For example, audio/video systems, control systems, and network applications. In the past, huge advances in technology and frequency scaling allowed the majority of computer applications to increase performance without requiring structural changes or custom hardware acceleration.
First, they targeted CPUs and looked for higher acceleration through frequency scaling. Then, they increased the number of processors to 8 or 16 to scale performance. With that, companies started looking at multicore solutions. However it was not an easy task for programmers to target multicore solutions. Then came along GPUs and they provided a massively parallel array solution of
these smaller cores. You can see that the trend slowly points towards more programmability and parallelism, which leads us to FPGAs.
iW-RainboW-G17M-Q7 supports OpenCL programming model
OpenCL was originally developed by Apple and is now managed by a large, industry-wide consortium. Let’s look at OpenCL in more detail.
OpenCL is a programming model for software engineers and a methodology for a system architect or engineering management. It is based on standard ANSI C (C99) with extensions, to add parallelism. OpenCL also includes an API, a standard interface for the CPU to communicate with the hardware accelerator. A key benefit of OpenCL is that it is a portable, royalty-free open standard, which is a key differentiator versus NVIDIA’s CUDA model. The OpenCL model allows any CPU to communicate with any hardware accelerator. It’s up to the individual CPU and hardware accelerator vendors to abstract away vendor specific implementation in order to meet conformance testing.
Using the model, the host CPU offloads performance-intensive functions to the hardware accelerator in the form of kernels.
Overview of OpenCL model: Here is a closer look at how OpenCL could work with a CPU communicating with an FPGA as an accelerator.
The software engineer writes their C code and uses a Standard C compiler on their host CPU of choice. Most of the code in the system is Standard C code running on the host CPU. The software engineer writes some functions in OpenCL C that runs through an OpenCL compiler.
An OpenCL application consists of a host program and kernel code. The host program is pure software written in Standard C. Any Standard C compiler is able to compile this host program, for example, Microsoft Visual Studio or GCC. Here, the line items in blue in the host code tell the processor to execute the kernel – more specifically, to copy the data from the host processor into the accelerator, which is the FPGA. It asks the FPGA to run a particular kernel and then copy the data back from the FPGA to the host.
Benefits of OpenCL in altera FPGA
Productivity: Leveraging the open standard dramatically simplifies FPGA development by enabling teams to design their systems and algorithms in a high-level C-based framework when targeting FPGAs. OpenCL provides customers a significant time-to-market advantage compared to traditional FPGA development flows that require the user to design in a lower level hardware description language. This leads to shorter architecture and design exploration cycles and faster time to market. OpenCL increases productivity by allowing designers to write programs that execute across heterogeneous platforms, including CPUs, GPUs, and FPGAs.
Performance: OpenCL looks to solve the hardware and software design flow in a different manner. When looking at an embedded system, the CPU is often the heart of the system for basic control logic. This can be a external processor or soft processor within the FPGA. The accelerator is often a “slave” to the CPU and increases performance when performance cannot be met in software running on a CPU. OpenCL attempts to preserve the software paradigm and looks to abstract away the hardware accelerator piece by using an open standard of the C language. The compiler and runtime routines distribute the workloads depending on the characteristics of the accelerator.
Performance per watt: The FPGA fabric offers high flexibility to minimize the power usage. Designers can use only logic elements as needed to generate custom hardware for the kernel, resulting in inherently lower power. Also, OpenCL generates custom hardware for your kernel, that is, it maps the hardware to your algorithm!
More about iW-RainboW-G17M-Q7: Refer the following link: http://www.iwavesystems.com/iwave-new-cyclone-v-soc-based-som-overview
For more information and/or to buy one of these boards, please contact – email@example.com
S. Abdul Raseeth Ansari - Senior Engineer (Software)
iWave Systems Technologies Pvt. Ltd.